Rajeev Chandrasekhar: Centre Will Review DLI Scheme, Check if Norms Need Tweaks

Minister of State for Electronics and IT Rajeev Chandrasekhar said the government will review the Design Linked Incentive (DLI) scheme to check if the norms need to be modified.

This scheme aims to support 100 companies involved in product design in the semiconductor space as part of a Rs 76,000-crore scheme to develop the country’s semiconductor ecosystem.

The minister has stated the programme will continue to support all product design projects and start-ups, among other things.

“Whether the DLI norms need to be modified… We have got some feedback from this conference that maybe the DLI has been designed to be very narrow. Maybe there is a cap on funding that is too restrictive. We will examine all that,” he added, while speaking at the Semicon India 2022 conference.

Chandrasekhar told the media that the Rs 76,000-crore package includes a $10-million package for the ecosystem, and design, as well as innovation.

“Talent is a very important part of the ecosystem. There is a need to sort of redesign some of those pieces, we will do it,” he further added.

However, at the event, the Ministry of Electronics and Information Technology announced the appointment of Prof Rao Tummala of Georgia Tech University in the United States to the India Semiconductor Mission’s Advisory Committee.

DESIGN LINKED INCENTIVE SCHEME

From smartphones to automobiles, semiconductors are a major part of all industries. After the pandemic hit the world, it was understood there is a need to reduce the dependency on China’s semiconductor industry and there should be more options to avoid supply chain obstacles in the future.

The National Policy on Electronics for 2019 intends to establish the country as a global hub for Electronics System Design and Manufacturing (ESDM), as well as a thriving semiconductor chip design ecosystem.

The government believes that India is well-positioned to attain self-reliance and technology leadership in the semiconductor design sector, with a talent pool that includes 20% of the world’s semiconductor design engineers and thousands of chips designed each year in the country.

The DLI scheme was announced by the Ministry of Electronics and Information Technology to address the challenges faced by the domestic semiconductor design industry to not only move up the value chain, but also to strengthen the country’s semiconductor chip design ecosystem.

As the Nodal Agency, the Centre for Development of Advanced Computing (CDAC) is in charge of implementing the DLI scheme.

Over a five-year period, the DLI scheme seeks to provide financial incentives as well as design infrastructure assistance for semiconductor designs for integrated circuits, chipsets, system on chips, systems & IP cores, and semiconductor-linked designs.

The objectives behind this scheme include:

• Nurturing and facilitating the growth of domestic companies, startups and MSMEs.

• Achieving significant indigenisation in semiconductor content and IPs involved in the electronic products deployed in the country, thus facilitating import substitution and value addition in the electronics sector.

• Strengthening and facilitating access to semiconductor design infrastructure for startups and MSMEs.

In terms of eligibility, domestic enterprises, startups and MSMEs involved in semiconductor design or semiconductor-connected design will receive financial incentives and design infrastructure support.

For a period of three years after claiming incentives under the scheme, approved applicants must maintain their domestic status—that is more than 50% of the capital in it is beneficially owned by resident Indian citizens and/or Indian companies that are ultimately owned and controlled by resident Indian citizens.

Additionally, it should be noted that the DLI scheme allows for:

• Reimbursement of up to Rs 30 lakh per application for MPW (multi-project wafer) fabrication of design and post-silicon validation activities.

• Reimbursement of up to 50% of eligible expenditure for designing semiconductor goods up to Rs 15 crore per application.

• Reimbursement of 6% to 4% of net sales of designed semiconductor goods over 5 years up to Rs 30 crore.

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